P.Latha, Dr. S.Ramasamy and K.Vigneshraja
For the common applications such as frequency generation, clock recovery, clock synchronisation, a Phase locked loop architecture will be generally used. To get a more stable operation Delay locked loops can be preferably used. This paper presents a comparative approach for the design of delay locked loops with application specific performance and low power consumption. Various phase detectors are compared here and a modified delay cell is proposed and the same is being used with various PD. A justification is brought about for using various PD for the respective applications. A comparison of DLLs using the normal and the modified delay cell are also presented here. A basic problem in DLL such as dead-zone problem is also addressed in this work. The figure of merit (FOM) is also calculated here and this work achieves a good FOM of 73.A Multiplexing architecture is also proposed with two different application specific DLLs combined together. The DLL architectures are implemented in Cadence Virtuoso schematic editor using UMC180nm. In addition, a frequency multiplying scheme using DLL is also presented here.
Dynamic PFD * PFD - GDI * Static and Dynamic Delay cell * Figure of merit, Multiplexing Architecture