Abhishek Agrawal, Nikhil Saxena
In this current paper execution of forward body biased True Single Phase Clock (FBBTSPC) and forward body biased extended True Single Phase Clock (FBBETSPC) are investigated. The delay of FBBTSPC and FBBETSPC are analyzed, simulated, executed and compared with the existing TSPC and ETSPC. A high speed divide-by-2 unit of frequency divider divide by two with the body biased is proposed and validated that this frequency divider divide by two can operate with higher frequency of 4 GHz stably on a 180 nm technology. This frequency divider divide by two with the body bias design can be widely used in Communication data analysis probe systems.
CMOS integrated circuit, D ?ip-?op (DFF), frequency divider, frequency synthesizer, high-speed digital circuit, true single-phase clock (TSPC) ,Extended true single-phase clock (E-TSPC),HSPICE